FIG. 1 illustrates a prior art memory system that includes multiple integrated circuit memory devices 120 coupled to a memory controller 110 via a bidirectional communication channel 140. Because each memory device 120 consumes physical space along the channel, the number of memory devices that can be coupled to the channel 140, and to some extent the storage capacity of the memory system, is limited by the length of the channel 140. The length of the channel 140 is itself limited by a number of practical considerations. For example, signals attenuate as they propagate down the channel 140, constraining the channel length to one that provides a tolerable signal level at the memory IC farthest from the controller 110. Similarly, channel capacitance increases with channel length, limiting the frequency response of the channel. Accordingly, the channel length usually must be limited to support the desired operating frequency of the memory system.
One technique for increasing the number of memory devices that can be used in a memory system without unacceptable loss in signaling margin or frequency response is to use buffering circuits to segment the communication path into multiple smaller channels. Unfortunately, buffers add latency that can be problematic, particularly in synchronous memory systems which rely on deterministic timing relationships. For example, in some memory systems, memory operations are pipelined by transmitting commands in the intervening time between transmission of an earlier command (e.g., a read command) and responsive transmission of the corresponding data (e.g., the read data). When buffers are positioned along the channel's length, however, the time intervals between command and response transmissions vary arbitrarily depending on the positions of the addressed memory devices (i.e., memory devices positioned downstream from one or more buffers or repeaters exhibit greater effective response delay than memory devices coupled directly to the memory controller). This significantly complicates command pipelining.
Thus, it is desirable to provide a memory subsystem that can support a large number of memory devices without degrading the reliability and performance of the memory system.